Switched capacitor networks are widely used in the design of electronics circuits in view of their ability to simulate a resistive load in a circuit. Using a switched capacitor Csw, switched at a frequency fsw, an equivalent resistance of Req can be realised where Req=1/(fsw×Csw). It is well known that in the fabrication of semiconductor integrated circuits, absolute precision of resistance values is not easily achievable whereas absolute precision of capacitance values is well within the control of the most semiconductor fabrication processes. For this reason, the use of switched capacitor circuits in analogue semiconductor circuit design, in situations where precise resistance values are required, is of particular importance.
Precise voltage reference circuits known as “bandgap reference circuits” are today well known and widely available. An example of such a precision bandgap reference circuit is described by D. Susak in U.S. Pat. No. 5,900,773. However the generation of a precise and stable current reference is a more difficult task. The availability of precision current reference generators is necessary for achieving accuracy in applications requiring sensors (e.g. hall element biasing), data converters (e.g. current steering DAC), etc.
Such current reference circuits can be realised using a switched capacitor, a comparator, a voltage reference and a reference clock in a mixed-signal closed loop circuit as is described in US Patent Application Publication 2006/0119422A1, Semiconductor Device Including Current Control Circuit of Reference Current Source, Sakurai et al., Jun. 8, 2006. This circuit has a drawback in that it is sensitive to delay in the comparator, thus leading to significant accuracy shortcomings due to variations in fabrication process, power supply variation and temperature variations.
While an analog buffer circuit based on switched capacitors is described by Cheol-Min et al. in United States Patent Application Publication No. 2005/0258997 A1, this circuit provides a copy of an input voltage with a fixed gain of 1 whereas an amplifier capable of amplifying and integrating a differential error signal would be required to solve the problem of providing a precision current reference generator.
In European Patent Application Publication No. 1,712,973 A2, Moro et al. describe a traditional constant-gm bias current generation circuit wherein the resistive element is directly replaced by its switched capacitor equivalent network together with a buffer capacitor. The main objective of this circuit is not so much to provide a precise absolute current reference, but rather to bias analog circuits for significantly constant performance (which depends on gm/C) by adapting the bias current to process and temperature variations. This circuit suffers from a number of inaccuracies which will be described below, preventing this circuit from being useful as a high precision current reference generator.
Another important building block in analogue and mixed signal circuit design is an oscillator. Normally, in order to build an accurate oscillator, a crystal or a ceramic resonator would be used. This leads to bulky and expensive solutions which are not very flexible due to the fact that they usually have preset frequencies corresponding to the frequency of available crystals or ceramics. Using a switched capacitor network with a controllable oscillator and a divider in a closed loop configuration a very accurate and flexible oscillator can be realised. An example of such a circuit is described by T. R. Viswanathan, S. Murtuza, V. H. Syed and M. Staszel, in “Switched-Capacitor Frequency Control Loop”, IEEE Journal of Solid State circuits, Vol. 17, Issue No. 4, August 1982, pp. 774-778.
FIG. 1a illustrates the manner in which a switched capacitor (CSW) and an amplifier (AMP) are generally used in circuits inspired by the work of Viswanathan et al. to obtain a desired voltage across the switched capacitor (CSW), and thus the desired current flow. In this circuit, a switched capacitor (CSW) is used in a feedback circuit with an operational amplifier (AMP) configured to respond to the difference between a reference voltage (VR) and the voltage across the switched capacitor network at point NB. The difference thus detected is used to control the amount of current in the switched capacitor.
The above design suffers from some inaccuracies, which will now be described with reference to the waveform in FIG. 1b. In a first phase (ph1), the switched capacitor is connected to the operational amplifier (AMP). Since the input of the operational amplifier (NB) has a buffer capacitor (CB) connected in parallel with the switched capacitor (CSW), at the moment the switched capacitor (CSW) is connected to the operational amplifier (AMP), the voltage at the input of the operational amplifier (NB) drops due to the parallel combination of the switched capacitor (CSW) and the buffer capacitor (CB). The current source (IB) charges the capacitor pair (CSW and CB) up until the end of the first phase (ph1). In a second phase (ph2), the switched capacitor (CSW) is decoupled from the operational amplifier (AMP) and discharged. The result is that the operational amplifier input (NB) is subject to a sawtooth waveform whose slope during the first phase (ph1) is slightly less than the slope during the second phase (ph2) due to the extra capacitance from the switched capacitor (CSW) in the first phase.
It can be shown that for correct operation of the above circuit, a regulation loop including the operational amplifier (AMP) must have a bandwidth which is significantly lower than the switching frequency. Under these conditions, the loop responds approximately to the time-average of the differential voltage at the input of the amplifier. Thus the time-average voltage at node NSW is regulated through the feedback loop to be equal to the reference voltage (VR).
It is worth noting that the switched capacitor (CSW) is charged to the voltage reached at the end of the first phase (ph1), which we will refer to as Vcharge, and then discharged during the second phase (ph2). However, since the sawtooth waveform at node NSW is not perfectly symmetrical, due to the different slopes during the first and second phases, the actual time-average of the voltage at node NSW is greater than the voltage reached at the end of the first phase (ph1) by a non-zero positive amount which we will refer to as an offset voltage (Voffset). In addition, the voltage drop across the switch (S1) due to its parasitic resistance further contributes to the offset voltage (Voffset). Furthermore, any timing discrepancies between the first and second phases will lead to an unbalanced duty cycle and will yet further contribute to the offset voltage (Voffset).
The charge transferred during a period is equal to Vcharge×CSW, which corresponds to an equivalent current of I=Vcharge×CSW×fsw where fsw is the switching frequency. We have shown above that, once stabilization of the feedback loop is achieved, Vcharge is not exactly equal to the reference voltage (VR). More specifically Vcharge=VR−Voffset. Thus the equivalent current flow is I=(VR−Voffset)×CSW×fsw instead of the desired value of VR×CSW×fsw. The amount of offset (Voffset) depends on the switch and op-amp characteristics, which change with process, power supply voltage and temperature, leading to an inaccurate and unstable current flow.
One way to minimize the offset (Voffset) would be to increase the value of the buffer capacitor (CB), such the sawtooth ripple at node (NB) would be minimized. This simple solution would however consume a large chip area if the circuit were to be integrated onto a semiconductor chip. In addition, a resulting pole at node (NB) would be moved to a lower frequency, conflicting with the regulation loop's main dominant pole and leading to difficulties in achieving loop stability.
Another dynamic amplifier is described by Vittoz in U.K. Patent Application Number 2,095,946 A, This circuit is widely known and is generally well-used in the industry. However, the amplifier circuit described in the present invention is self-biasing in such a way that the output voltage in an amplification phase (cf ph1) is nominally equal to the voltage reached in a preparation phase (cf ph2), thus eliminating the residual input offset even when using low-gain devices typically available in advanced short-channel semiconductor technologies.